1. Field of the Invention
The present invention is directed in general to voltage regulation in an integrated circuit. In one aspect, the present invention relates to an on-chip method and system for regulating and calibrating the supply or reference voltage of an integrated circuit memory device.
2. Description of the Related Art
Many integrated circuit devices, such as a non-volatile memory device, use an on-chip reference voltage generator to generate an internal reference voltage from an external reference voltage. In one example, the internal reference voltage is generated by shifting the output of a bandgap voltage generator or some other temperature insensitive voltage generator. Referring to FIG. 1, a commonly-used reference voltage generator circuit 1 is constructed with an operational amplifier 2 and a voltage follower circuit 3 which consists of a transistor 17 and resistor 19 placed in the feedback path of the operational amplifier 2. The reference voltage generator circuit 1 receives an external reference voltage Vref at the negative input node 10 of the op amp 2, and generates an output voltage Vout at the source follower 18. However, there can be a number of errors introduced that can impair the resulting accuracy of the output voltage Vout. Such errors can arise when a bandgap voltage is used for the input reference voltage Vref if the bandgap voltage is not well suited for the regulation circuit. Errors can also be caused by variations in resistor matching, and from other differences that can arise when the same circuit is formed on separate die. In the voltage generator circuit 1 shown in FIG. 1, these error sources are represented by the Verror term at the negative input node 10, where the term Vref′ represents the desired reference voltage to be generated by the voltage generator circuit 1. Another source of error in the generated output voltage Vout is caused by the opamp offset voltage Voffset that represents the difference in op amp performance as compared to an “ideal” op amp 14. In the voltage generator circuit 1 shown in FIG. 1, this error source is represented by the Voffset source 11 that is connected in series with the positive input terminal of the “ideal” op amp 14, though it can be placed in series with either terminal and its value will be a random variable. The offset error Voffset appears at the output Vout and sums with the reference voltage Vref, Vout=Vref+Voffset.
As circuits are increasingly designed with smaller and smaller voltages (e.g., low power applications), it is becoming increasingly important to generate internal reference voltages that are accurate to within a percent, particularly as the smaller voltages are used which reduce the room for error when generating the internal reference voltage(s). While different solutions have been proposed for addressing the different types of error source, none have proven entirely satisfactory. For example, errors contained in the input voltage Verror can be addressed by adjusting or trimming the resistor divider 19 during test by digitally selecting one of the switched taps in the resistor divider 19. The tap selection can be determined individually for each device by monitoring the Vout signal and searching for an optimal tap, but this approach requires costly test time. The tap selection may also be generalized for all devices by characterizing all devices, but selecting a tap based on characterization places a burden on processing, and requires resources to monitor the validity of the choice throughout the life of the product. Thus, neither method is optimal in the production environment. While automated reference voltage regulation circuits have been proposed, such as described in U.S. Pat. No. 6,738,298 to Cioaca et al, they do not address all of the error sources (such as the opamp offset voltage error source) and also suffer from undue circuit complexity. Indeed, common offset suppression techniques increase circuit size and complexity, and are one major reason that analog circuitry does not scale with decreasing feature size.
Accordingly, there is a need for an improved system and methodology for efficiently regulating a reference voltage generator circuit to remove error sources from the input voltage source and from the opamp offset voltage. There is also a need for an automatic reference voltage regulation circuit which overcomes the problems in the art, such as outlined above. Further limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.